The present invention relates to a nonvolatile, integrated-circuit memory array such as an electrically-erasable, electrically-programmable read-only-memory (EEPROM) array and, more particularly, to prevention of over-erasure in a flash-type EEPROM array.
EEPROMs employing single-transistor memory cells, using hot-carrier injection for programming and Fowler-Nordheim tunnelling for erasure are described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM," S. Mukherjee et al., IEDM 1985 (p. 616-619) and in (b) "A 90ns 100K Erase/Program Cycle Megabit Flash Memory," V. Kynett et al., ISSCC 1989 (p. 140-141). The topic of reference (a) is also discussed in U.S. Pat. No. 4,698,787.
In particular, the invention relates to predicting and minimizing read errors resulting from over-erasing the floating-gates of nonvolatile memory arrays. An EEPROM cell is over-erased when an excessive number of electrons is removed from its floating gate during an erasing operation. The source-drain path of an over-erased EEPROM cell is conductive with the control gate and the source or drain at the same electric potential.
Nonvolatile memory arrays include floating-gate memory cells arranged in rows and columns. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path (channel) under the charged floating gate nonconductive when a chosen wordline select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is positively charged, is neutrally charged, or is slightly negatively charged, such that the source-drain path under the non-programmed floating gate is conductive when the same chosen wordline select voltage is applied to the control gate. The conductive state is read as a "one" bit.
Each column and row of an EEPROM array may contain thousands of cells. The sources of each cell in a row are, for example, connected to a source line and each source line is connected to a common source-column line. The drains of each cell in a column are connected to a separate bitline (drain-column line). The control gates of each cell in a row are connected to a wordline. Prior to the first programming operation, or perhaps after erasure by ultraviolet light, the source-drain paths of the cells begin to conduct at a uniform control-gate threshold voltage Vt because the floating gates are neutrally charged (having neither an excess of electrons nor a deficiency of electrons). The initial uniform threshold voltage Vt may be, for example, +2.5 V between control gate and source. Adjustment of the initial uniform threshold voltage Vt may be made by altering the doping of the channel regions of the cells during manufacture.
After programming, the source-drain paths of the programmed cells have control-gate threshold voltages Vt distributed over a range of perhaps between +6 V to +9 V, for example. The distribution of threshold voltages Vt among individual cells is caused by processing variations, including variations in the tunnel oxide thicknesses, the areas of tunnelling regions and in the coupling ratios of the control-gate voltages to the floating gates, as well as variations in the programming voltages applied to individual cells.
After electrical erasure of the cells, the threshold voltages Vt of the erased cells may, for example, be distributed over a range from perhaps +0.5 V to +2.5 V with the majority of the cells having erased threshold voltages Vt near +1.5 V, the range depending on the localized variations in the tunnel oxide thickness, the areas of tunnelling regions, the capacitive coupling ratios between wordlines and floating gates, and the strengths of the erasing pulses. Using lower-strength erasing pulses, the range may be from perhaps +1.5 V to +3.5 V with the majority of the cells having erased threshold voltages Vt near +2.5 V. With higher-strength erasing pulses applied, the distribution may range from perhaps -0.5 V to +1.5 V with the majority of cells having erased threshold voltages Vt near +0.5 V. Cells with erased threshold voltages Vt less than that set during the manufacturing process have deficiencies of electrons (or have net positive charges) on the floating gates. The excess of positive charges on the floating gates causes the channel regions under such gates to be enhanced with electrons. Cells with negative threshold voltages are called "over-erased" cells.
In general, the extent of channel doping, the programming pulse strength, the erasing pulse strength and other factors are chosen such that the source-drain path of a cell will either be conductive or non-conductive when applying a chosen wordline select voltage to the control gate. The select voltage must have a value somewhere between the highest erased-threshold-voltage value of erased cells and the lowest programmed-threshold-voltage value of the programmed cells. In many types of memory arrays, the channel doping, programming/erasing voltages and other factors are chosen such that the wordline select voltage is equal to the available chip supply voltage Vcc, which may be +5 V. With +5 V applied to the control gates, the source-drain paths of all of the properly erased cells are conductive only if those cells have threshold voltages Vt below the +5 V select voltage. Similarly, the source-drain paths of all of the properly programmed cells are non-conductive only if those cells have threshold voltages Vt greater than the +5 V select voltage.
A common failure mechanism in flash EPROM technology is caused by over-erasure of cells. One of the problems associated with EEPROMs of the single-transistor, non-split-gate type is the difficulty of reading memory arrays after some of the cells have been over-erased, becoming depletion-mode devices. Because the channel regions of the over-erased cells are connected in parallel with all of the source-drain paths of other cells in a column, inaccuracies during reading operation may occur where the stored data in those columns is short-circuited by the over-erased cells. At least some of the over-erased cells may be conductive because the excessive positive charge on the floating gates causes the channel regions to invert from P-type to N-type. Therefore, the over-erased cells conduct current even with their control gates grounded. If the depletion of one of the over-erased cells is severe, the leakage current through that cell will cause every cell, including programmed cells, in the same column to appear erased (conducting current when positive voltage is applied to the control gate). In many cases, the over-erased cells hinder programming operations.
One method for eliminating the problem of over-erasure is to construct cells with pass gates, or split gates, in which the channel between source and drain includes two series sections, one section having the control gate separated from the channel region by the gate dielectric, the second region having the floating gate separated from the channel region by the gate dielectric. However, such memory cells require more area on a silicon chip than do cells without split gates. Other methods include use of negative voltages, use of doping techniques, and application of low-energy programming pulses.
The problem of over-erasure may also be lessened checking after each flash erasing operation to see whether or not any of the cells are close to over-erasure. The check may be performed with a small positive voltage on the control gates of the cells. Circuits and methods for such checking are described in U.S. Pat. No. 4,460,982 issued Jul. 17, 1984; U.S. Pat. No. 4,841,482 issued Jun. 20, 1989; U.S. Pat. No. 4,860,261 issued Aug. 22, 1989; U.S. Pat. No. 4,875,188 issued Oct. 17, 1989; and U.S. Pat. No. 5,053,990 issued Oct. 1, 1991. Prior-art circuits and methods used to sense susceptibility to over-erasure are described later herein. The prior-art circuits and methods have required comparison circuits using off-chip current references. Because of the capacitance of such external testing circuitry, the process of testing memories to determine depletion or near depletion of cells is slower than necessary. Prior-art memories have included reference columns used as current references during reading operations. However, use of such reference column produces an unreliable comparison current for use in depletion sensing.
Accordingly, there is a need for a circuit and method to provide for fast and reliable detection of depleted or nearly-depleted cells in a column. Preferably, the circuit and method would also permit the extent of depletion to be quantified easily and quickly.